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IS61C12816
128K x 16 HIGH-SPEED CMOS STATIC RAM
FEATURES
* High-speed access time: 12, 15, and 20 ns * CMOS low power operation -- 450 mW (typical) operating -- 250 W (typical) standby * TTL compatible interface levels * Single 5V 10% power supply * Fully static operation: no clock or refresh required * Three state outputs * Industrial temperature available * Available in 44-pin SOJ package and 44-pin TSOP(II)
ISSI
(R)
DECEMBER 2000
DESCRIPTION The ISSI IS61C12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C12816 is packaged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin TSOP(II).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
1
IS61C12816
PIN CONFIGURATIONS
44-Pin SOJ
A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC
ISSI
44-Pin TSOP(II)
A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC
(R)
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2
Write
ICC1, ICC2
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
IS61C12816
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -65 to +150 1.5 20 Unit V C W mA
ISSI
(R)
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1 2 3 4 5
OPERATING RANGE
Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Speed -12 -15, -20 -12 -15, -20 VCC 5V 5% 5V 10% 5V 5% 5V 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND - VIN - VCC GND - VOUT - VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.2 -0.5 -2 -2 Max. -- 0.4 VCC + 0.5 0.8 2 2 Unit V V V V A A
6 7 8 9
Notes: 1. VIL (min.) = -3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC ISB1 Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE * VIH , f = 0 VCC = Max., CE * VCC - 0.2V, VIN * VCC - 0.2V, or VIN - 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. -12 Min. Max. 280 -- -- -- -- -- -- 300 50 55 10 15 -15 Min. Max. 260 -- -- -- -- -- -- 290 50 55 10 15 -0 2 Min. Max. 235 -- -- -- -- -- mA 255 50 55 10 15 mA Unit
10 11
mA
ISB2
12
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
3
IS61C12816
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -12 Min. Max. 12 -- 3 -- -- -- 0 0 3 -- 0 0 -- 12 -- 12 6 6 -- 6 -- 6 6 -- -15 Min. Max. 15 -- 3 -- -- 0 0 0 3 -- 0 0 -- 15 -- 15 7 6 -- 6 -- 7 6 -- -20 Min. Max. 20 -- 4 -- -- 0 0 0 3 -- 0 0 -- 20 -- 20 9 8 -- 8 -- 9 8 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB tLZB
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
AC TEST LOADS
480 5V
480 5V
OUTPUT 30 pF Including jig and scope 255
OUTPUT 5 pF Including jig and scope 255
Figure 1 4
Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
IS61C12816
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ISSI
(R)
1 2
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
3 4
READ CYCLE NO. 2(1,3)
tRC
5
tOHA
ADDRESS
tAA
OE
tDOE tHZOE
6 7
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
8
HIGH-Z
tLZB
DOUT
9 10 11 12
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
5
IS61C12816
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End
(2)
ISSI
-12 Min. Max. 12 9 9 0 0 9 9 6 0 -- 3 -- -- -- -- -- -- -- -- -- 6 -- -15 Min. Max. 15 10 10 0 0 10 10 7 0 -- 3 -- -- -- -- -- -- -- -- -- 7 -- -20 Min. Max. 20 12 12 0 0 12 12 9 0 -- 3 -- -- -- -- -- -- -- -- -- 9 -- Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE
WE LOW to High-Z Output
tLZWE(2) WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
IS61C12816
AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2)
ISSI
tWC
(R)
1
ADDRESS
tSCE tHA
2 3
tPWB
CE
LB, UB
tAW tPWE
4 5 6
tSD tHD tSA
WE
WRITE(1)
DIN
tHZWE tLZWE
UNDEFINED HIGH-Z UNDEFINED HIGH-Z
7 8 9 10 11 12
DOUT
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00
7
IS61C12816
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 12 12 15 15 20 20 Order Part No. IS61C12816-12T IS61C12816-12K IS61C12816-15T IS61C12816-15K IS61C12816-20T IS61C12816-20K Package Plastic TSOP(II) 400-mil Plastic SOJ Plastic TSOP(II) 400-mil Plastic SOJ Plastic TSOP(II) 400-mil Plastic SOJ
ISSI
(R)
Industrial Range: -40C to +85C
Speed (ns) 12 12 15 15 20 20 Order Part No. IS61C12816-12TI IS61C12816-12KI IS61C12816-15TI IS61C12816-15KI IS61C12816-20TI IS61C12816-20KI Package Plastic TSOP(II) 400-mil Plastic SOJ Plastic TSOP(II) 400-mil Plastic SOJ Plastic TSOP(II) 400-mil Plastic SOJ
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 12/19/00

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